Digital communication systems must use accurate clock recovery mechanisms to achieve the lowest possible error rate in the received information. The clock recovery scheme must not only determine the correct data rate, but also must determine the optimum point at which to sample the received signal. Any deviation from the optimum sampling point increases the effect of inter-symbol interference and decreases the signal-to-noise ratio. This is particularly important in highly efficient modulation schemes, such as Multilevel Sub-Band Coding, where many symbols represent 256-level data. Multi-phase signal correlators determine the optimum sampling point to within the reciprocal of the number of phases used in the correlations times the symbol period. Any attempt to increase the precision of these correlators results in extensive additional hardware or additional processing time if the correlations are done by a digital signal processor (DSP) such as, for example, the DSP56001 available from Motorola, Inc., 1301 East Algonquin Road, Schaumburg, II 60196. In addition, as the recovered clock drifts with respect to the transmitted symbol rate, the recovered sample point will drift within its range of precision. As a result, there is a need for an improved symbol synchronization circuit.